1. Field of the Invention
The present invention relates to a test circuit for logic circuits which fetches data from a register connected to an interface circuit. The semiconductor circuit performs logical operations and stores results in the register.
2. Description of the Prior Art
FIG. 1 is a block diagram showing a conventional semiconductor circuits such as, a one-chip microcomputer. The semiconductor circuit includes logic circuits for receiving data from a register connected to an interface circuit. An operation is performed, the result of which is stored in the register.
In the figure, numeral 1 denotes an input terminal. An instruction code 101 is input on input terminal 1 by control of a CPU, (not shown).
An instruction decoder 2 decodes the instruction code 101 input from the input terminal 1. A decoded result of instruction decoder 2 is input to a register control circuit 3 and interface control circuit 4 as a control signal 102.
The register control circuit 3 outputs a control signal 103 for controlling data transmissions between a register 5 and an internal bus 8. These data transmitted are controlled according to the control signal 102 received from the instruction decoder 2.
The interface control circuit 4 outputs a control signal 104 which controls an interface circuit 6. Control of interface circuit 6 is determined according to the control signal 102 received from the instruction decoder 2.
The register 5 is connected to the internal bus 8 and controlled by the control signal 103 received from the register control circuit 3. The data stored in register 5 is output to the internal bus 8. Further, data on internal bus 8 can be stored in register 5. Register 5 is connected to an internal logic circuit 20 as such as an ALU.
The internal logic circuit 20 fetches data stored in the register 5. A prescribed logical operation is performed on the data and the result is again stored in the register 5.
The interface circuit 6 is connected to the internal bus 8 and controlled by the control signal 104 received from the interface control circuit 4. Depending upon the state of control signal 104, data is either input from an external terminal 7 to the internal bus 8, or output from the interface circuit 6 to the external terminal 7.
Operations of a semiconductor circuit including such conventional logic circuits are as follows.
When the instruction code 101 is input to the input terminal 1, the instruction code is decoded by the instruction decoder 2 from which the control signal 102 is output.
Now, suppose that the instruction code 101 is a data transfer instruction code. In that case the instruction code stores data in the register 5 from the external terminal 7 of the interface circuit 6 via the internal bus 8. Alternatively, register 5 may output the data to the external terminal 7 via the internal bus 8 and interface circuit 6.
The control signal 102 is input to the register control circuit 3 and interface control circuit 4. The register control circuit 3 outputs the control signal 103 in response to receiving the control signal 102 to the register 5. The interface control circuit 4 outputs the control signal 104 responsive to the control signal 102 to the interface circuit 6.
The instruction code 101 input to the input terminal 1 may be an instruction for outputting data to the external terminal 7 from the register 5. In that case, register 5 outputs the data to the internal bus 8 according to the control signal 103 input from the register control circuit 3. The interface circuit 6 fetches the data from the internal bus 8 and outputs to the external terminal 7 according to the control signal 104 received from the interface control circuit 4. Likewise, the instruction code input to the input terminal 1 may be an instruction for setting data to the register 5 from the external terminal 7. In this case, the interface circuit 6 fetches the data from the external terminal 7 and outputs it to the internal bus 8 according to the control signal 104 received from the interface control circuit 4. The register 5 fetches and stores the data from the internal bus 8 according to the control signal 103 received from the register control circuit 3. The data stored in the register 5 is input to the internal logic circuit 20.
The conventional semiconductor circuit including the logic circuit has the configuration described hereinabove. It may used for checking, for example, the operation of internal logic circuit 20 or for determining whether the operating function is normal. To perform checking it is necessary to execute a prescribed program in the CPU, (not shown), to transfer the dat to the internal logic circuit 20 from the external terminal 7 of the interface circuit 6. The result is output to the external terminal 7 of the interface circuit 6 from the internal logic circuit 20.
In other words, the instruction code of data transfer is input to the input terminal 1 at each time to execute the data transfer to the register 5 from the interface circuit 6 and to the interface circuit 6 from the register 5.
In view of above circumstances, inventions disclosed in Japanese Patent Application Laid-Open Nos. 208476 (1984), 168051 (1986) and 132182 (1987) have been proposed.
In Japanes Patent Application Laid-Open No. 208476 (1984), "a test circuit is described for forming a test mode signal. The test circuit receives serial data and supplies a test pattern signal directly to the internal logic circuit from a predetermined input terminal. The circuit also sends out a signal of an internal logic circuit to a predetermined output terminal. The test circuit is incorporated to improve the test effect without increasing the number of external terminals". In the same invention, "the inputted serial data is set at a signal level higher than the ordinary signal level so as" not to increase the level on the external terminals.
Thus, in the invention disclosed in Japanese Patent Application Laid-Open No. 208476 (1984), the test circuit requires various parts such as a level detecting circuit for detecting a level of the serial data to be inputted, a shift register for holding it and a decoder. However, since the test circuit is built in the semiconductor circuit for use in the supplier side, and for users, it consumes just an actual capacity of the semiconductor circuit. Therefore, a test circuit which is too complicated with too many component parts is not preferable.
The invention disclosed in Japanese Patent Application Laid-Open No. 168051 (1986) relates to a test circuit of a RAM of single-chip microcomputer. Therefore, for checking whether the operation result of the logic circuits such as ALU etc. is normal, a specific address of the RAM must be accessed at a suitable timing to take out the data.
The invention of Japanese Patent Application Laid-Open No. 132182 (1986) relates to a test circuit of a large scale integrated circuit, which is divided into a plurality of blocks so as to be tested separately respectively. Thus, it is not suitale for checking whether the operation result of a specific logic circuit is correct.